As scaling of integrated circuits continues, non-planar device structures such as the FinFET are becoming increasingly attractive as device options because of their good short channel characteristics. A fin-type field effect transistor (“FinFET”) is a type of transistor that has source and drain regions in contact with a channel region contained in a semiconductor fin. Nearly all FinFETs are fabricated as double-gate FETs with opposing first and second gate conductors on either sidewall of the fin. FinFETs are discussed in greater detail in U.S. Pat. No. 6,413,802 to Hu et al., which is hereby incorporated by reference in its entirety.
In the following discussion, crystalline silicon is used as an example and the crystalline planes of the crystalline silicon are denoted by the commonly used Miller indices (see definition in Ashcroft/Mermin, Solid State Physics, pp. 91-93, Cornell University, 1976, which is hereby incorporated by reference in its entirety). For example, (100), (010), and (001) are all equivalent in a cubic crystal by virtue of symmetry. Similarly (110), (101) and (011) are all equivalent crystal planes.
To maximize the CMOS performance it is desirable to pair p-FinFETs having a (110) oriented channel surface with n-FinFETs having a (100) oriented channel surface. When using conventional substrates where the notch is aligned with the (110) direction and the wafer's surface is parallel to the (100) direction, the fins of the p-FinFETs are generally etched parallel to the notch to obtain a (110) oriented channel while the fins for n-FinFETs are etched at a 45 degrees off the notch to obtain a (100) oriented channel. Similarly, when the wafer's surface is (110), the fins forming the p-FinFETs and the fins forming the n-FinFETs are perpendicular to each other (i.e. the fins are forming a right angle).
However, due to lithographic constraints and the drive to obtain denser layouts, it is desired that the fins of the CMOS pair be parallel. This requirement generally leads to the use of CMOS pairs in which both devices have the same channel crystal orientation and usually leads to sub-optimal performance of the devices. Stated differently, current fabrication methods that form parallel fins use CMOS pairs having the same channel crystal orientation, which results in sub-optimal performance of the device pairs.
Therefore a need exists to overcome the problems with the prior art as discussed above.